Abstract
Turbo codes are the best coding scheme for error correction in
high-speed wireless systems because they achieve the highest coding
gain. However, the implementation of various Turbo Decoders suffers from
a large delay and high power consumption. For this reason, they are not
suitable for many applications like mobile communication systems. In
this paper, a comparative study has been made and various decoding
algorithm used in SISO Turbo Decoders have been analyzed viz. MAP,
Log-MAP, Max-Log-MAP and SOVA, to overcome this drawback. It presents
the discussion of complexity and performance trade-offs of SISO Turbo
decoders.
Introduction
In communication systems, signal degradation due to noise translates to
an abundance of bit errors. Turbo codes are one of the error correcting
codes used. Turbo codes invented in 1993 have become one of the
important research topics in communication and coding society since
their performance is close to the theoretical limit. The use of these
codes has been proposed for several applications where highly reliable
transmission is required at very low signal to noise ratio (SNR). In
spite of the extensive literature on Turbo codes, the hardware
implementation of turbo codes is happened to be a very challenging
topic, mainly due to iterative nature of the decoding process. So, the
need of low power, high speed and low area turbo decoders are very much
felt in present communication systems. The various features which
constitute Turbo Codes can be summarized as follows:
A. Turbo Encoder: The code structure of Turbo code is formed by two constituent convolutional encoders concatenated in parallel through a pseudo-random interleaver. As shown in fig.1, encoder generates parity bits from two simple recursive convolutional codes. The information bit (x) is also sent uncoded with two parity bits (p1 & p2), generated from two encoders. The key innovation of turbo codes is an interleaver (I), which permutes the original bit (x) before input to the second encoder. The permutation, which allows that input sequences for which one encoder produces low weight code words, will usually cause the other encoder to produce high weight code words. Thus even though the constituent code are individually weak, the combination is surprisingly powerful. Thus three bits (x, p1, p2) are transmitted for each bit with code rate 1/3. Each encoder consists of a shift register augmented with generator function- AND & XOR gates. The constraint length K for the encoder indicates the number of times each input bit in the shift chain influences a parity output. B. Turbo Decoder: After x, p1 & p2 are transmitted through a communication channel, they ultimately arrive at the Turbo decoder as y, u & v. Due to channel noise, the received values may not match their transmitted values. The Turbo decoder attempts to reconstruct transmitted values through a series of decoding steps. Decoding strategy is based on the exchange of soft information between SISO (Soft Input Soft Output) component decoders in an iterative fashion. The iterative turbo decoder structure is shown in fig.2. Decoding is split in two steps in correspondence with the two encoding stages. The interleaver permutes the data bit to support the error correction algorithm. The output from one decoder is fed into the other decoder through an interleaver/deinterleaver to help the later decoder make a better decoding decision in subsequent decoding iterations. Multiple iterations are required before the decoder converges to a final result. After a pre specified number of decoding iterations, the final decision is made in the decision block by combining the outputs from both decoders. CRC (Cyclic Redundancy Check) technique can be employed to stop the iterations once the proper decoded stream has been recovered. The component decoder takes quantized data from channel and gives out quantized confidence levels/probabilities for each decoded bit. They are therefore termed Soft Input, Soft Output (SISO) decoders. The a-priori information is the soft inputs to the channel decoder and the a-posteriori information is the soft output of the channel decoder. The most widely used soft-values at the output of decoder are log-likelihood ratios - LR (LLR’s). They are represented as follows: (1) If the LLR of a bit is positive, it implies that the bit is most likely to be a ‘1’ and if it is negative, the bit is most likely to be ‘0’. The various SISO Turbo decoders are: Maximum A-priori (MAP), Log-MAP, Max-log-MAP and Soft Output Viterbi Algorithm (SOVA). (a) MAP, Log-MAP & Max-Log-MAP Algorithm: The MAP algorithm provides not only the estimated sequence, but also the probabilities for each bit that has been decoded correctly. Assuming binary codes are to be used, the MAP algorithm gives, for each decoded bit xk in step k, the probability that this bit was +1 or –1, given the received distorted symbol sequence y 0 = (y0, y1, y2, …., yN)This is equivalent to finding the likelihood ratio (2) Where P {xk, y0} i =+1, -1 is the a posteriori probability (APP) of xk,. Computation of P{ xk, y0 } is done by determining the probability to reach a certain encoder state m after having received k symbols y = (y0, y1, y2, …., yk-1): (3) and the probability to get from encoder state m’ to the final state in step N with symbols yk+1: (4) The probability of the transition m m’ using the source symbol xk, under knowledge of received symbol yk, is called : (5) The probabilities k (m) and k+1(m’) are computed recursively over k (m, m’, xk) which are a function of the received symbols and the channel model as below: (6) (7) Knowing these values for each transition m m’, the probability of having sent the symbol xk in step k the sum of all paths using the symbols xk in step k. With ( xk) being the set of all transitions with symbol xk, we can write (8) Thus, we can say that MAP algorithm is complex because to evaluate the likelihood value of a decoded bit it require many additions and multiplications. The decoding complexity of the MAP algorithm has been reduced in Log-MAP algorithm by operating it in the log domain. Taking the negative logarithm of k (m), k+1(m’), k (m, m’, xk) and k values from the MAP algorithm we have: (9) (10) (11) (12) Using the above equations, we rewrite eq. (6) & (7) as: (13) (14) Dk (m, m’, xk) is calculated as: (15) Where are the received signal and estimated signal over a Gaussian channel respectively, P(xk) is the a-priori probability of bit xk and 2 is the noise variance. Finally the log likelihood ratio value is calculated as: (16) All the summation in eq.(13), (14) and (16) can be represented in the form of a ‘E’ operator which is defined as follows: a E b = -ln(e-a + e-b). This can be rewritten as min (a, b)-ln (1+e-a-b). The log-MAP Decoder is divided into four major blocks. These are the branch metric calculation (BMC) block, the forward state metric calculation (FSMC) block, reverse state metric calculation (RSMC) block and log-likelihood ratio calculation (LLRC) block. The block diagram is shown in fig.3. The forward state metric unit uses the branch metrics obtained directly from the BMU to calculate the forward state metrics, and the backward state metric unit uses the reversed branch metrics from the branch metric storage to calculate the reverse state metrics. An important part of the state metric calculation block is the implementation of adders and ‘E’ operand. The FSMC and RSMC blocks are identical except for the direction of recursion. The branch metrics are added to the state metrics and then the minimum is found between the two obtained competing path metrics. The difference between the two path metrics is stored in a lookup table to obtain the value of the function: f (a-b) = ln (1+e-a-b ). Thus the add-compare-select and the E-operations are carried out in ACSE (add-compare-select and E-operation) block. For the forward state metrics the state metric value for state 00 is initialized to zero and the remaining states to the maximum possible value. For the reverse state metrics, if the final state is unknown all the initial state metrics are set to zero, otherwise they are initialized in the same way as the forward state metrics. The suboptimal implementation of Log-MAP decoder called the Max-Log-MAP decoder is obtained by using the approximation to evaluate the log-APP in eq. (16). The Max-Log-MAP decoder associates with ith bit, the minimum difference between the metric associated with the ML path and the best path that differs from the ML path in the input of the ith trellis section. A high value of reliability implies that the ML path and the next best path are far apart, hence there is a lower probability of choosing the other path and making a bit error. A bit with high reliability is more likely to have decoded correctly than a bit with low reliability. (b) SOVA based Turbo Decoder: The SOVA algorithm considers only two most likely (ML) paths - and . The soft output is based on the difference in path metric between these two ML paths, that trace back to complementary bit decisions, and , as shown in fig.4 Figure 4: Two ML paths It is assumed that the absolute values of the path metrics, Mα and Mβ, dominate over that of other paths, such that the probability of selecting β over α (i.e. the wrong decision) is given by eq. (17). (17) The log likelihood of a correct output by the SOVA decoder is given in eq. (18). (18) The system architecture of this implementation is shown in fig.5 Figure 5: System Architecture of SOVA Decoder The branch metric generator, compare select-add (CSA), and L-step survivor memory unit (SMU) form the building blocks of a conventional Viterbi decoder. The CSA is a retimed and transformed version of the more common addcompare- select (ACS) structure, and provides higher throughput rate at a lower area cost than traditional loop unrolling methods. In addition to providing a path decision at each iteration, the CSA of the SOVA decoder is also required to output the difference in path metric difference. The decisions and the metric differences are cached into an array of L-step FIFO buffers. The delayed decisions are used in the M-step path equivalence detector (PED) to determine the similarity between each pair of competing decisions obtained through a j-step trace back, j{1,2,...,M}. Finally, the output decisions from the SMU are used to select the delayed metric difference and the equivalence outputs corresponding to the most-likely state. These signals are input to a reliability measure unit (RMU), which outputs the minimum path metric difference reflecting complementary bit decisions, and . COMPARATIVE STUDY OF VARIOUS MAP ALGORITHMS & SOVA • All MAP decoders are based on BCJR (Bahl-cocke-Jelinek-Raviv) algorithm and SOVA is based on Viterbi algorithm. • MAP algorithm tries to minimize the code word error by maximizing the probability, which is a maximum likelihood (ML) algorithm while SOVA attempts to maximize the a-posteriori probabilities (APP) of the individual bit. • MAP algorithm involves extensive multiplication and logarithmic computation, which are complicated in hardware implementation, but SOVA has relatively low computational complexity. • MAP algorithm takes all paths into consideration and generates the sum of probabilities of all paths in the estimation. Its performance is optimal in terms of bit error rate (BER). On other hand SOVA produces the soft output by considering only two ML paths. Hence the extrinsic information depends strongly on the choice of the two paths. It yields in inferior soft output than MAP algorithm. LITERATURE SURVEY Most of the literature is focused on the optimization of power and speed. Atluri & Arslan have proposed VLSI architecture for low power implementation of a Log-MAP decoder through the minimization of memory size for the storage of reverse state metrics. The technique resulted in 88% reduction in memory utilization at the expense of 13% increase in branch metric storage. This provides a net power reduction of 35%. Gord Allan has worked on VLSI implementation of a modified Log-MAP decoder that can process data at up to 60 Mbps, consuming 15 mW of power and 24000 gates. Bougard, Giulietti, Perre & Catthoor have developed and prototyped a novel decoder architecture whose throughput is up to 75.6 Mbps with an energy efficiency of 1.45 nJ/bit/iterations. Weifeng & Ting have proposed a new structure of Log-MAP Turbo decoder. Their results of tests on Altera FPGA have proved that proposed structure could achieve good performance (BER-10-5 at SNR-1.5dB) with high throughput (440 Kbps), which meet the 384 Kbps requirements in 3G standard. Ituero, Vallejo & Mujtaba have proposed Application Specific Instruction Set Processor (ASIP) architecture for Max-Log-MAP algorithm. They achieved a high concurrency level, which reduces the total execution time. Vogt & Finger have given a method for improving the Max-Log-MAP algorithm for Turbo decoders. They applied a simple scaling factor to the extrinsic information, which improved the decoding performance by about 0.2 to 0.4 dB. Engling Yeo et all have implemented two 8-state, 7-bit Soft Output Viterbi decoders in 4 mm2 chip operates at 1.8V, 400 mW and verified to decode at 500Mb/s. Jian Liang et all have presented a dynamically reconfigurable FPGA-based Turbo decoder which has been optimized for power consumption. They derived Adaptive SOVA and through experimentation they shown that up to a 52% power savings can be achieved. CONCLUSION After the deep study and analysis of various Turbo decoders and from the literature survey, we strongly felt that the circuit complexity and power consumption of Turbo decoder implementations can often be prohibitive for power constraint systems. Although research work is going on in this area to optimize the Turbo decoder implementation for low power consumption and high speed, but still more work is required. The design of low cost and low power Turbo decoders is the need of an hour. So, we are planning to do work towards optimization of decoding algorithm for Turbo codes not only on the basis of power and speed but also for small area using VLSI technology. REFERENCES 1. Atluri, I., Arslan, T. (2003)., Low Power VLSI Implementation of Map Decoder for Turbo Codes through Forward Recursive Calculation of Reverse State Metrics.Proc. of SOC Conference-2003, IEEE International. 2. Avudainayagam, A., Shea, J. M., Roongta, A., On Approximating the Density Function of Reliabilities of the Max-Log-MAP Decoder. Proc. of Communication Systems & Applications 422 (2004 ). 3. Bougard, B., Giulietti, A., Van der Perre V., Catthoor F., A Low-Power High Speed Parallel Concatenated Turbo-decoding Architecture. Proc. of GLOBECOM-2002, IEEE, vol.1 549-553 (2002). 4. Ituero, P., Lopez-Vallejo, M., Mujtaba, S.A., A Configurable Application Specific Processor for Turbo Decoding. Thirty-Ninth Asilomar Conference on Signals, Systems and Computers. October 28 - November 1, 1356 – 1360 (2005). 5. Liang, J., Tessier, R., Goeckel, D. A Dynamically-Reconfigurable, Power-Efficient Turbo Decoder. Proc. of 12th Annual IEEE Symposium on FCCM 91-100 (2004). 6. Vogt, J., Finger, A. Improving the Max-Log-MAP Turbo Decoder. IEE Electronics letters, vol.6 (2000). . 7. Weifeng, Xu, Ting, Zhou. (n.d.). Implementation of a new structure of Turbo decoder with 384Kbps in 3G. http://www-unix.ecs.umass.edu/~wxu/turbo.pdf. 8. Yeo, E., Pakzad, P., Liao, E., Nikolic, B., Anantharam, V. (n.d.). Iterative Decoding Algorithms and their Implementation. http://www.ucop.edu/research/micro/02_03 /02_054.pdf. BIOGRAPHY 1. Dr. Seema Verma is a researcher and working as a Senior faculty in Department of Computer Science & Electronics, Banasthali Vidyapith. Her areas of interest include Communication, Error Control Coding, TURBO CODES, OFDM, MIMO, MT-CDMA, Channel Modeling, VLSI design of communication systems etc. She is the coinvestigator of the research projects given by AICTE & ISRO. She is a research guide announced by UGC. She has many papers to her credit in many National & International Conferences. 2. 2. Mrs. Usha Ladge: She is a faculty member in Electronics in the Department of Computer Science & Electronics. Her areas of research includes VLSI implementation of Communication Systems.
A. Turbo Encoder: The code structure of Turbo code is formed by two constituent convolutional encoders concatenated in parallel through a pseudo-random interleaver. As shown in fig.1, encoder generates parity bits from two simple recursive convolutional codes. The information bit (x) is also sent uncoded with two parity bits (p1 & p2), generated from two encoders. The key innovation of turbo codes is an interleaver (I), which permutes the original bit (x) before input to the second encoder. The permutation, which allows that input sequences for which one encoder produces low weight code words, will usually cause the other encoder to produce high weight code words. Thus even though the constituent code are individually weak, the combination is surprisingly powerful. Thus three bits (x, p1, p2) are transmitted for each bit with code rate 1/3. Each encoder consists of a shift register augmented with generator function- AND & XOR gates. The constraint length K for the encoder indicates the number of times each input bit in the shift chain influences a parity output. B. Turbo Decoder: After x, p1 & p2 are transmitted through a communication channel, they ultimately arrive at the Turbo decoder as y, u & v. Due to channel noise, the received values may not match their transmitted values. The Turbo decoder attempts to reconstruct transmitted values through a series of decoding steps. Decoding strategy is based on the exchange of soft information between SISO (Soft Input Soft Output) component decoders in an iterative fashion. The iterative turbo decoder structure is shown in fig.2. Decoding is split in two steps in correspondence with the two encoding stages. The interleaver permutes the data bit to support the error correction algorithm. The output from one decoder is fed into the other decoder through an interleaver/deinterleaver to help the later decoder make a better decoding decision in subsequent decoding iterations. Multiple iterations are required before the decoder converges to a final result. After a pre specified number of decoding iterations, the final decision is made in the decision block by combining the outputs from both decoders. CRC (Cyclic Redundancy Check) technique can be employed to stop the iterations once the proper decoded stream has been recovered. The component decoder takes quantized data from channel and gives out quantized confidence levels/probabilities for each decoded bit. They are therefore termed Soft Input, Soft Output (SISO) decoders. The a-priori information is the soft inputs to the channel decoder and the a-posteriori information is the soft output of the channel decoder. The most widely used soft-values at the output of decoder are log-likelihood ratios - LR (LLR’s). They are represented as follows: (1) If the LLR of a bit is positive, it implies that the bit is most likely to be a ‘1’ and if it is negative, the bit is most likely to be ‘0’. The various SISO Turbo decoders are: Maximum A-priori (MAP), Log-MAP, Max-log-MAP and Soft Output Viterbi Algorithm (SOVA). (a) MAP, Log-MAP & Max-Log-MAP Algorithm: The MAP algorithm provides not only the estimated sequence, but also the probabilities for each bit that has been decoded correctly. Assuming binary codes are to be used, the MAP algorithm gives, for each decoded bit xk in step k, the probability that this bit was +1 or –1, given the received distorted symbol sequence y 0 = (y0, y1, y2, …., yN)This is equivalent to finding the likelihood ratio (2) Where P {xk, y0} i =+1, -1 is the a posteriori probability (APP) of xk,. Computation of P{ xk, y0 } is done by determining the probability to reach a certain encoder state m after having received k symbols y = (y0, y1, y2, …., yk-1): (3) and the probability to get from encoder state m’ to the final state in step N with symbols yk+1: (4) The probability of the transition m m’ using the source symbol xk, under knowledge of received symbol yk, is called : (5) The probabilities k (m) and k+1(m’) are computed recursively over k (m, m’, xk) which are a function of the received symbols and the channel model as below: (6) (7) Knowing these values for each transition m m’, the probability of having sent the symbol xk in step k the sum of all paths using the symbols xk in step k. With ( xk) being the set of all transitions with symbol xk, we can write (8) Thus, we can say that MAP algorithm is complex because to evaluate the likelihood value of a decoded bit it require many additions and multiplications. The decoding complexity of the MAP algorithm has been reduced in Log-MAP algorithm by operating it in the log domain. Taking the negative logarithm of k (m), k+1(m’), k (m, m’, xk) and k values from the MAP algorithm we have: (9) (10) (11) (12) Using the above equations, we rewrite eq. (6) & (7) as: (13) (14) Dk (m, m’, xk) is calculated as: (15) Where are the received signal and estimated signal over a Gaussian channel respectively, P(xk) is the a-priori probability of bit xk and 2 is the noise variance. Finally the log likelihood ratio value is calculated as: (16) All the summation in eq.(13), (14) and (16) can be represented in the form of a ‘E’ operator which is defined as follows: a E b = -ln(e-a + e-b). This can be rewritten as min (a, b)-ln (1+e-a-b). The log-MAP Decoder is divided into four major blocks. These are the branch metric calculation (BMC) block, the forward state metric calculation (FSMC) block, reverse state metric calculation (RSMC) block and log-likelihood ratio calculation (LLRC) block. The block diagram is shown in fig.3. The forward state metric unit uses the branch metrics obtained directly from the BMU to calculate the forward state metrics, and the backward state metric unit uses the reversed branch metrics from the branch metric storage to calculate the reverse state metrics. An important part of the state metric calculation block is the implementation of adders and ‘E’ operand. The FSMC and RSMC blocks are identical except for the direction of recursion. The branch metrics are added to the state metrics and then the minimum is found between the two obtained competing path metrics. The difference between the two path metrics is stored in a lookup table to obtain the value of the function: f (a-b) = ln (1+e-a-b ). Thus the add-compare-select and the E-operations are carried out in ACSE (add-compare-select and E-operation) block. For the forward state metrics the state metric value for state 00 is initialized to zero and the remaining states to the maximum possible value. For the reverse state metrics, if the final state is unknown all the initial state metrics are set to zero, otherwise they are initialized in the same way as the forward state metrics. The suboptimal implementation of Log-MAP decoder called the Max-Log-MAP decoder is obtained by using the approximation to evaluate the log-APP in eq. (16). The Max-Log-MAP decoder associates with ith bit, the minimum difference between the metric associated with the ML path and the best path that differs from the ML path in the input of the ith trellis section. A high value of reliability implies that the ML path and the next best path are far apart, hence there is a lower probability of choosing the other path and making a bit error. A bit with high reliability is more likely to have decoded correctly than a bit with low reliability. (b) SOVA based Turbo Decoder: The SOVA algorithm considers only two most likely (ML) paths - and . The soft output is based on the difference in path metric between these two ML paths, that trace back to complementary bit decisions, and , as shown in fig.4 Figure 4: Two ML paths It is assumed that the absolute values of the path metrics, Mα and Mβ, dominate over that of other paths, such that the probability of selecting β over α (i.e. the wrong decision) is given by eq. (17). (17) The log likelihood of a correct output by the SOVA decoder is given in eq. (18). (18) The system architecture of this implementation is shown in fig.5 Figure 5: System Architecture of SOVA Decoder The branch metric generator, compare select-add (CSA), and L-step survivor memory unit (SMU) form the building blocks of a conventional Viterbi decoder. The CSA is a retimed and transformed version of the more common addcompare- select (ACS) structure, and provides higher throughput rate at a lower area cost than traditional loop unrolling methods. In addition to providing a path decision at each iteration, the CSA of the SOVA decoder is also required to output the difference in path metric difference. The decisions and the metric differences are cached into an array of L-step FIFO buffers. The delayed decisions are used in the M-step path equivalence detector (PED) to determine the similarity between each pair of competing decisions obtained through a j-step trace back, j{1,2,...,M}. Finally, the output decisions from the SMU are used to select the delayed metric difference and the equivalence outputs corresponding to the most-likely state. These signals are input to a reliability measure unit (RMU), which outputs the minimum path metric difference reflecting complementary bit decisions, and . COMPARATIVE STUDY OF VARIOUS MAP ALGORITHMS & SOVA • All MAP decoders are based on BCJR (Bahl-cocke-Jelinek-Raviv) algorithm and SOVA is based on Viterbi algorithm. • MAP algorithm tries to minimize the code word error by maximizing the probability, which is a maximum likelihood (ML) algorithm while SOVA attempts to maximize the a-posteriori probabilities (APP) of the individual bit. • MAP algorithm involves extensive multiplication and logarithmic computation, which are complicated in hardware implementation, but SOVA has relatively low computational complexity. • MAP algorithm takes all paths into consideration and generates the sum of probabilities of all paths in the estimation. Its performance is optimal in terms of bit error rate (BER). On other hand SOVA produces the soft output by considering only two ML paths. Hence the extrinsic information depends strongly on the choice of the two paths. It yields in inferior soft output than MAP algorithm. LITERATURE SURVEY Most of the literature is focused on the optimization of power and speed. Atluri & Arslan have proposed VLSI architecture for low power implementation of a Log-MAP decoder through the minimization of memory size for the storage of reverse state metrics. The technique resulted in 88% reduction in memory utilization at the expense of 13% increase in branch metric storage. This provides a net power reduction of 35%. Gord Allan has worked on VLSI implementation of a modified Log-MAP decoder that can process data at up to 60 Mbps, consuming 15 mW of power and 24000 gates. Bougard, Giulietti, Perre & Catthoor have developed and prototyped a novel decoder architecture whose throughput is up to 75.6 Mbps with an energy efficiency of 1.45 nJ/bit/iterations. Weifeng & Ting have proposed a new structure of Log-MAP Turbo decoder. Their results of tests on Altera FPGA have proved that proposed structure could achieve good performance (BER-10-5 at SNR-1.5dB) with high throughput (440 Kbps), which meet the 384 Kbps requirements in 3G standard. Ituero, Vallejo & Mujtaba have proposed Application Specific Instruction Set Processor (ASIP) architecture for Max-Log-MAP algorithm. They achieved a high concurrency level, which reduces the total execution time. Vogt & Finger have given a method for improving the Max-Log-MAP algorithm for Turbo decoders. They applied a simple scaling factor to the extrinsic information, which improved the decoding performance by about 0.2 to 0.4 dB. Engling Yeo et all have implemented two 8-state, 7-bit Soft Output Viterbi decoders in 4 mm2 chip operates at 1.8V, 400 mW and verified to decode at 500Mb/s. Jian Liang et all have presented a dynamically reconfigurable FPGA-based Turbo decoder which has been optimized for power consumption. They derived Adaptive SOVA and through experimentation they shown that up to a 52% power savings can be achieved. CONCLUSION After the deep study and analysis of various Turbo decoders and from the literature survey, we strongly felt that the circuit complexity and power consumption of Turbo decoder implementations can often be prohibitive for power constraint systems. Although research work is going on in this area to optimize the Turbo decoder implementation for low power consumption and high speed, but still more work is required. The design of low cost and low power Turbo decoders is the need of an hour. So, we are planning to do work towards optimization of decoding algorithm for Turbo codes not only on the basis of power and speed but also for small area using VLSI technology. REFERENCES 1. Atluri, I., Arslan, T. (2003)., Low Power VLSI Implementation of Map Decoder for Turbo Codes through Forward Recursive Calculation of Reverse State Metrics.Proc. of SOC Conference-2003, IEEE International. 2. Avudainayagam, A., Shea, J. M., Roongta, A., On Approximating the Density Function of Reliabilities of the Max-Log-MAP Decoder. Proc. of Communication Systems & Applications 422 (2004 ). 3. Bougard, B., Giulietti, A., Van der Perre V., Catthoor F., A Low-Power High Speed Parallel Concatenated Turbo-decoding Architecture. Proc. of GLOBECOM-2002, IEEE, vol.1 549-553 (2002). 4. Ituero, P., Lopez-Vallejo, M., Mujtaba, S.A., A Configurable Application Specific Processor for Turbo Decoding. Thirty-Ninth Asilomar Conference on Signals, Systems and Computers. October 28 - November 1, 1356 – 1360 (2005). 5. Liang, J., Tessier, R., Goeckel, D. A Dynamically-Reconfigurable, Power-Efficient Turbo Decoder. Proc. of 12th Annual IEEE Symposium on FCCM 91-100 (2004). 6. Vogt, J., Finger, A. Improving the Max-Log-MAP Turbo Decoder. IEE Electronics letters, vol.6 (2000). . 7. Weifeng, Xu, Ting, Zhou. (n.d.). Implementation of a new structure of Turbo decoder with 384Kbps in 3G. http://www-unix.ecs.umass.edu/~wxu/turbo.pdf. 8. Yeo, E., Pakzad, P., Liao, E., Nikolic, B., Anantharam, V. (n.d.). Iterative Decoding Algorithms and their Implementation. http://www.ucop.edu/research/micro/02_03 /02_054.pdf. BIOGRAPHY 1. Dr. Seema Verma is a researcher and working as a Senior faculty in Department of Computer Science & Electronics, Banasthali Vidyapith. Her areas of interest include Communication, Error Control Coding, TURBO CODES, OFDM, MIMO, MT-CDMA, Channel Modeling, VLSI design of communication systems etc. She is the coinvestigator of the research projects given by AICTE & ISRO. She is a research guide announced by UGC. She has many papers to her credit in many National & International Conferences. 2. 2. Mrs. Usha Ladge: She is a faculty member in Electronics in the Department of Computer Science & Electronics. Her areas of research includes VLSI implementation of Communication Systems.
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