Design Rule for Minimizing Thermal Resistance
In A Non–Uniformly Powered Microprocessor
Abstract
Microprocessors continue to grow in capabilities, complexity and
performance. The current generation of microprocessors integrates
functional components such as logic and level two (L2 )cache memory into
the microprocessor architecture. The functional integration of the
microprocessor has resulted in better performance of the microprocessor
as the clock speed and the instruction execution time has increased.
However, the integration has introduced a layer of complexity to the
thermal design and management of microprocessors. As a direct result of
function integration, the power map on a microprocessor is highly
non-uniform and the assumption of a uniform heat flux across the chip
surface is not valid. Previous work [1] has been done to minimize the
thermal resistance of the package by optimizing the distribution of the
non-uniform powered functional blocks with a specific power matrix. The
objective of this paper is to come up with a design rule in general for
functional block distribution in a non – uniformly powered
micro-architecture. In order to model the non-uniform power dissipation
on the silicon chip, the chip surface area is divided into different
cases such as 3 x 3, 4x 4 etc. of power matrix with a matrix space
representing a distinct functional block with a constant heat flux.
Finally, using a FEM
code, an optimization of the positioning of the functional blocks
relative to each other was carried out in order to minimize the junction
temperature Tj. The best possible Tjmax reduction could thus be found.
In reality (and at a later date) constraints must be placed regarding
the maximum separation of any 2 (or more) functional blocks to satisfy
electrical timing and compute performance requirements A design rule for
minimizing thermal resistance will be developed for any number of
functional blocks for a given non uniformly powered microprocessor. The
commercial finite element code ANSYS® is used for this analysis.
Keywords
Non-uniform power, optimization, thermal resistance
Introduction
As the performance of microprocessor increases, the need
to supply data and instructions to the core processor increases
accordingly. In the past, these information, which normally reside in
main memories are channeled to microprocessor via the bus, a parallel
set of interconnects running between the microprocessor and the memory.
In the recent Intel product generations, improved integrated circuit
(IC) density makes it practical to integrate the Level Two (L2) cache
into the microprocessor architecture. This integrated L2 cache stores
the frequently used data thereby reducing the frequency of accessing
information from the external main memories. Consequently, this speeds
up data execution and enhances microprocessor performance. Although the
integration of L2 cache into microprocessor architecture renders
definite design advantages, it also poses other challenges in the
thermal design of next generation processors, especially for those with
significantly large integrated L2 cache. One of the challenges is to
design a thermal solution that meets the thermal performance of
microprocessor with non-uniform power density within the silicon die.
The non-uniform power distribution occurs when the central processing unit (CPU) or core processor region of the die dissipates a significant fraction of the total power while the other cache regions of the die dissipate little or no power. This non-uniformity of power distribution results in a large die temperature gradient, with localized hot spots that are expected to affect the processor performance, product reliability as well as yield. This phenomenon [2] was reported in the design of Pentium® III XeonTM processor for 4-way and 8-way server systems where significantly large L2 cache was integrated to the silicon design. Previous work [1,2,3] has been done in understanding the thermal solutions for the non-uniform power distribution within the silicon die. Numerical and analytical work [4,5,6,7] also has been done for non-uniform power distribution study focusing on various approaches. Previous work [1] has been done to minimize the thermal resistance of the package by optimizing the distribution of the non uniform powered functional blocks with a specific power matrix .The objective of this paper is to come up with a design rule in general for functional block distribution in a non – uniformly powered architecture. Typically, a die is divided into 30x30 matrix in order to account for the highly non-uniform nature of the die power distribution. This, however, will result in 900 design variables, which will be impossible to model with a standard workstation. In this study, in order to model the non-uniform power dissipation on the silicon chip, the chip surface area is divided into a various cases such as 3 x 3, 4x 4, 5 x 5, 8 x 8, 10 x 10, 12 x 12 and 15 x 15 of power matrix with a matrix space representing a distinct functional block with a constant heat flux. Finally, using a FEM code, an optimization of the positioning of the functional blocks relative to each other was carried out in order to minimize the junction temperature Tj. With these many power maps, trend for the data is evaluated which helps to draw some design guideline for a typical die configuration i.e. 30 x 30. Thus A design rule for minimizing thermal resistance will then be developed for any number of functional blocks for a given non uniformly powered micro-architecture. Nomenclature h Convective heat transfer coefficient, W/m2 K k Thermal Conductivity, W/m K P Total dissipated power, W T Temperature, °C Subscripts a Ambient j Junction Background Technical challenges in the thermal management of microprocessors arise from two causes such as increasing power dissipation, which is associated with increasing performance; and the need to cool regions of local power concentrations, which are called as “hot spots.” Generally, thermal management features are integrated in packages to spread heat while transporting heat from the die to the heat sink. The heat sink in turn dissipates heat to the local environment. The thermal management problem is one of ducting the Thermal Design Power (TDP) from the die surface at temperature Tj to the ambient at temperature Ta. The temperature difference (Tj – Ta) is expected to slowly reduce over time since Tj can typically be forced lower by reliability and performance expectations, and Ta can be forced higher due to heating of the inside box air caused by increased integration and shrinking box sizes. Figure 1 shows TDP trends over time, and a simple scaling projection indicates that the TDP will increase as a function of time, which reduce microprocessor power, occur. Thus the thermal challenge arises from the fact that increasing values of TDP have to be ported between a diminishing temperature differences. This challenge is exacerbated by another very important factor. On-die power distribution is typically not uniform. With increasing performance, the non-uniformity of on-die power distribution there are regions of the die dissipating high heat flux densities. These regions are commonly referred to as hot spots. Since the temperature of the hot spot can often affect performance and will always govern the overall reliability of the silicon, maintaining the hot spot temperature below certain limits is a requirement in thermal design. This leads to two undesirable consequences such as the focus on cooling the hot spot leads to a general over-design in the microprocessor cooling solution and the non-uniformity in the heat source limits the total amount of heat that can be managed by a thermal solution. The overall problem is graphically illustrated in Figure 2, which shows a plot of the overall cooling capability of different thermal solutions as a function of the Density Factor (DF), as a measure of the impact of power non-uniformity. [8] Description of a problem To model the optimization of maximum junction temperature on a given silicon chip with non-uniform power dissipation using a commercial FEM code. The different specific cases of power maps that will be used for the optimization are 4 x 4, 5 x 5, 6x 6, 8 x 8, 10 x 10, 12 x 12 and 15 x 15. In order to model the non-uniform power dissipation on the silicon chip, the chip surface area is divided into a given matrix with a matrix space representing a distinct functional block with a constant heat flux. Finally, using a FEM code, an optimization of the positioning of the functional blocks relative to each other was carried out in order to minimize the junction temperature Tj. A Schematic diagram of a typical attachment shown in Figure 3 is used for the analysis. It has a heat sink of 64 x 64 x 6.35 attached to the spreader of 31 x 31 x 1.8 to the silicon die with the help of TIM 1 and TIM2 with a thickness of 0.25. Geometry is created using given dimensions for Die, Spreader, Heat sink and TIMs. Die is divided into a matrix of above mentioned power maps to study the optimization of given power maps as described. A steady state thermal analysis is carried out to calculate the maximum junction temperature (Tj) for given power maps for both the cases. Mesh sensitivity analysis is carried out with temp varies in the range of +/- 1 ° C; coarse meshing is used for the analysis. Parameters such as thick nesses of TIM1 and TIM 2, thermal conductivities of TIMs and convective transfer coefficient are calculated to satisfy the given package conditions. All the material properties are applied as per the material property data. Total power of 115 W is applied over a die as per the given power maps. A (h) of 1200 W/m2 °C is used on the top of package for the analysis. Once baseline cases for given non-uniform power maps are carried out, an optimization study is carried out to see the effect of non-uniform power on the maximum junction temperature. Percentage variation in the optimized temperature is plotted against baseline temperature. Design guideline will then be suggested for any number of power maps. Tool Ansys Workbench is used for the analysis and optimization study. Modeling Methodology Maximum junction temperature is simulated for the different power maps as mentioned above as baseline case. Initially optimization study is carried out for 4 x 4 and 6 x 6 power maps to define the number of functional blocks for any number of power maps [1]. For optimization study a functional blocks of 4, 6 and 12 different individual powers are used as a design variable for 6 x 6 power map. Blocks of 16 design variables are used for the case of 4 x 4 power map. Design explorer is used to analyze the optimization study. Functional block is a group of number of design variables (In this paper, different individual powers in a given power map). This analysis has no constraints placed on the redistribution of functional blocks. Figure 6 shows a solid model of divided die for four different cases. Figure 7 and 8 gives the different cases considered for optimization for two different power maps. A functional block of 4, 6 and 12 design variables can be seen on a 6 x 6 power map and 16-design variable in case of 4 x 4 power map as a test cases for optimization study. This study is then extended for all other power maps to get an optimized junction temperature. The best possible Tj max reduction could thus be found. In reality (and at a later date) constraints must be placed regarding the maximum separation of any 2 (or more) functional blocks to satisfy electrical timing and compute performance requirements. Ansys Design Xplorer is a powerful tool for designing and understanding the analysis response of parts and assemblies. Design Xplorer is based on Design of Experiment (DOE) and various optimization methods, and uses parameters as its basic language. These parameters can come from Simulation, Design Modeler, and various supported CAD systems. DOE is a technique used to determine the location of sampling points. There are several versions of design of experiment available in engineering literature. These techniques all have one common characteristic: they try to locate the sampling points such that the space of random input parameters is explored in the most efficient way, or obtain the required information with a minimum of sampling points. Sample points in efficient locations will not only reduce the required number of sampling points, but also increase the accuracy of the response surface that is derived from the results of the sampling points. Design Xplorer uses a central composite design, which combines one center point, points along the axis of the input parameters, and the points determined by a fractional factorial design. [9,10] Design parameters such as input, derived and response parameters are defined to start the optimization. Different powers are the input parameters and maximum junction temperature is the response parameter. Using the DOE method the number of design points is directly related to the number of selected input Parameters. No of design variables are usability variables, which depend on number of input parameters. Automatic design points are created using central composite design theory. Once it runs for the entire design points goal driven optimization is carried out to extract the desired results. In this case goal is to have summation of all the individual powers in an assigned functional block should be same with keeping the individual power distinct to lower down maximum junction temperature. Numbers of design variables are restricted to 18, which allow performing two different types of study on 6 x6 and 4 x 4 power maps. A combination study is carried out for the earlier one while first hand study is carried out for the later one. Once this study is carried out a graph of percentage variation change in optimized temperature is plotted against baseline case for different power maps. From this, guidelines are set for distribution of power, which will help to get comparable values of optimized temperature for a realistic power map i.e. 30 x 30. Following is a study shown for two typical cases. Case I: 6 x 6 Power map. As shown in the power map, functional blocks of 4, 6 and 12 are created to study its effect on the overall junction temperature. A combination of theses 3 methods will then be used to optimize the maximum junction temperature. These different cases are chosen randomly to account for variations of individual powers. Once data for individual cases of different functional blocks is extracted, a combination for best cases is selected to come up with optimized power map for 6 x 6. Case II: 4 x 4 power map for this power map, all the 16 different individual powers are grouped in a single functional block to optimize the design. This attempt will come up with design in a single attempt. Results and discussions Table 2 gives the various values of maximum junction temperature (baseline and optimized) with a percentage variation for all different power maps. Figure 9 and 11 shows the temperature distribution for original power map and optimized one for 6 x 6 case. Figure 10 and 12 shows the graph of power distribution after optimization study for 6 x 6 case as a test case. Original power map clearly shows the hot spots in the center with non-uniform temperature all over the area of the die. With optimized case, temperature is distributed more evenly over the area of the die. Figure 13 shows temperature distribution for optimized one for different cases such as 5,8,10 and 15. It can be seen that temperature distribution shows huge temperature drop within the chip after optimization. Figure 14 shows effect on maximum junction temperature for base and optimized cases for different power maps. Base line (original) temperature goes on increasing as the power map matrix number increases. This is possible due to the required uniform distribution of temperature for the higher power map matrices. Figure 15 shows effect on percentage variation change in optimized temperature on optimized temperature compared to baseline case. With the optimized temperature, range of 5 % to 13 % drop in temperature is achieved compare to original temperature for different cases of power maps. As the number of design variables increases, a significant drop in temperature can be possible for higher functional blocks. Increase in the percentage variation change in optimized temperature for ascending power maps is a key example of this fact. Interchanging locations of highest power with lowest power significantly lowers the maximum junction temperature. Low powers are distributed over periphery as compared to high powers. Groups of high powers, which are located near the center, are more responsible for optimization within the die. Functional blocks of wide range of powers are more effective as compared to blocks of same range. As power map matrix increases control over optimization enhances because of different levels of individual powers within that power map. High powers are distributed to various locations to form group of wide range of high and low powers. These design guidelines will be helpful to get the optimized junction temperature for a realistic power map case of 30 x 30 with 900 different functional blocks. Summary and Conclusion Thermal based optimization of functional block distributions in a non-uniform powered die is carried out using Ansys Workbench. In this study, in order to model the non-uniform power dissipation on the silicon chip, the chip surface area is divided into a various cases such as 3 x 3, 4x 4, 5 x 5, 8 x 8, 10 x 10, 12 x 12 and 15 x 15 of power matrix with a matrix space representing a distinct functional block with a constant heat flux. Finally, using a FEM code, an optimization of the positioning of the functional blocks relative to each other was carried out in order to minimize the junction temperature Tj. With these many power maps trend for the data is evaluated which helps to draw some design guideline for a typical die configuration i.e. 30 x 30. With the optimized temperature, range of 5 % to 13 % drop in optimized temperature is achieved compare to original temperature for different cases of power maps. As the number of design variables increases, a significant drop in temperature can be possible for higher functional blocks. Increase in the percentage variation change in optimized temperature for ascending power maps is a key example of this fact. Interchanging locations of highest power with lowest power significantly lowers the maximum junction temperature. Low powers are distributed over periphery as compared to high powers. Groups of high powers, which are located near the center, are more responsible for optimization within the die. Functional blocks of wide range of powers are more effective as compared to blocks of same range. As power map matrix increases control over optimization enhances because of different levels of individual powers within that power map. This analysis has no constraints placed on the redistribution of functional blocks. The best possible Tj max reduction could thus be found. In reality (and at a later date) constraints must be placed regarding the maximum separation of any 2 (or more) functional blocks to satisfy electrical timing and compute performance requirements. With following these design guidelines and key points further optimization study can be very effective for a realistic power map case of 30 x 30 with 900 different functional blocks. References 1. Abhijit Kaisare, Dereje Agonafer, A. Haji-shiekh, Greg Chrysler and Ravi Mahajan, “Thermal based optimization of functional block distributions in a non-uniformly powered die,” published in InterPACK conference, 2005. 2. Teck Joo Goh, A.N. Amir, Chia-Pin Chiu and J. Torresola, "Novel thermal validation metrology based on non-uniform power distribution for Pentium(R) III XeonTM cartridge processor design with integrated level two cache,"51st Electronic Components and Technology Conference, 2001, pp. 1181-1186. 3. Teck Joo Goh, "Thermal methodology for evaluating the performance of microelectronic devices with non-uniform power dissipation," 4th Electronics Packaging Technology Conference, 2002. pp. 312-317. 4. V. Gektin, Ron Zhang, M. Vogel, Guoping Xu and M. Lee, "Substantiation of numerical analysis methodology for CPU package with non-uniform heat dissipation and heat sink with simplified fin modeling," Thermal and Thermomechanical Phenomena in Electronic Systems, 2004, pp. 537-542 Vol.1 5. K.K. Sikka, "An analytical temperature prediction method for a chip power map," Semiconductor Thermal Measurement and Management Symposium, 2005, pp. 161-166 6. M.S. June and K.K. Sikka, "Using cap-integral standoffs to reduce chip hot-spot temperatures in electronic packages," Thermal and Thermomechanical Phenomena in Electronic Systems, 2002, pp. 173-178. 7. Zhiping Yu, D. Yergeau, R.W. Dutton, S. Nakagawa and J. Deeney, "Fast placement-dependent full chip thermal simulation," VLSI Technology, Systems, and Applications, 2001, pp. 249-252. 8. Ravi Mahajan, Raj Nair, V. Wakharkar, “ Emerging Directions for packaging technologies,” Intel Technology Journal, Q2, 2002 9. [S.G. Jagarkal, M.M. Hossain, D. Agonafer, M. Lulu and S. Reh, "Design optimization and reliability of PWB level electronic package," Thermal and Thermomechanical Phenomena in Electronic Systems, 2004, pp. 368-376 Vol.2. 10. Ansys Workbench (9.0) reference manual
The non-uniform power distribution occurs when the central processing unit (CPU) or core processor region of the die dissipates a significant fraction of the total power while the other cache regions of the die dissipate little or no power. This non-uniformity of power distribution results in a large die temperature gradient, with localized hot spots that are expected to affect the processor performance, product reliability as well as yield. This phenomenon [2] was reported in the design of Pentium® III XeonTM processor for 4-way and 8-way server systems where significantly large L2 cache was integrated to the silicon design. Previous work [1,2,3] has been done in understanding the thermal solutions for the non-uniform power distribution within the silicon die. Numerical and analytical work [4,5,6,7] also has been done for non-uniform power distribution study focusing on various approaches. Previous work [1] has been done to minimize the thermal resistance of the package by optimizing the distribution of the non uniform powered functional blocks with a specific power matrix .The objective of this paper is to come up with a design rule in general for functional block distribution in a non – uniformly powered architecture. Typically, a die is divided into 30x30 matrix in order to account for the highly non-uniform nature of the die power distribution. This, however, will result in 900 design variables, which will be impossible to model with a standard workstation. In this study, in order to model the non-uniform power dissipation on the silicon chip, the chip surface area is divided into a various cases such as 3 x 3, 4x 4, 5 x 5, 8 x 8, 10 x 10, 12 x 12 and 15 x 15 of power matrix with a matrix space representing a distinct functional block with a constant heat flux. Finally, using a FEM code, an optimization of the positioning of the functional blocks relative to each other was carried out in order to minimize the junction temperature Tj. With these many power maps, trend for the data is evaluated which helps to draw some design guideline for a typical die configuration i.e. 30 x 30. Thus A design rule for minimizing thermal resistance will then be developed for any number of functional blocks for a given non uniformly powered micro-architecture. Nomenclature h Convective heat transfer coefficient, W/m2 K k Thermal Conductivity, W/m K P Total dissipated power, W T Temperature, °C Subscripts a Ambient j Junction Background Technical challenges in the thermal management of microprocessors arise from two causes such as increasing power dissipation, which is associated with increasing performance; and the need to cool regions of local power concentrations, which are called as “hot spots.” Generally, thermal management features are integrated in packages to spread heat while transporting heat from the die to the heat sink. The heat sink in turn dissipates heat to the local environment. The thermal management problem is one of ducting the Thermal Design Power (TDP) from the die surface at temperature Tj to the ambient at temperature Ta. The temperature difference (Tj – Ta) is expected to slowly reduce over time since Tj can typically be forced lower by reliability and performance expectations, and Ta can be forced higher due to heating of the inside box air caused by increased integration and shrinking box sizes. Figure 1 shows TDP trends over time, and a simple scaling projection indicates that the TDP will increase as a function of time, which reduce microprocessor power, occur. Thus the thermal challenge arises from the fact that increasing values of TDP have to be ported between a diminishing temperature differences. This challenge is exacerbated by another very important factor. On-die power distribution is typically not uniform. With increasing performance, the non-uniformity of on-die power distribution there are regions of the die dissipating high heat flux densities. These regions are commonly referred to as hot spots. Since the temperature of the hot spot can often affect performance and will always govern the overall reliability of the silicon, maintaining the hot spot temperature below certain limits is a requirement in thermal design. This leads to two undesirable consequences such as the focus on cooling the hot spot leads to a general over-design in the microprocessor cooling solution and the non-uniformity in the heat source limits the total amount of heat that can be managed by a thermal solution. The overall problem is graphically illustrated in Figure 2, which shows a plot of the overall cooling capability of different thermal solutions as a function of the Density Factor (DF), as a measure of the impact of power non-uniformity. [8] Description of a problem To model the optimization of maximum junction temperature on a given silicon chip with non-uniform power dissipation using a commercial FEM code. The different specific cases of power maps that will be used for the optimization are 4 x 4, 5 x 5, 6x 6, 8 x 8, 10 x 10, 12 x 12 and 15 x 15. In order to model the non-uniform power dissipation on the silicon chip, the chip surface area is divided into a given matrix with a matrix space representing a distinct functional block with a constant heat flux. Finally, using a FEM code, an optimization of the positioning of the functional blocks relative to each other was carried out in order to minimize the junction temperature Tj. A Schematic diagram of a typical attachment shown in Figure 3 is used for the analysis. It has a heat sink of 64 x 64 x 6.35 attached to the spreader of 31 x 31 x 1.8 to the silicon die with the help of TIM 1 and TIM2 with a thickness of 0.25. Geometry is created using given dimensions for Die, Spreader, Heat sink and TIMs. Die is divided into a matrix of above mentioned power maps to study the optimization of given power maps as described. A steady state thermal analysis is carried out to calculate the maximum junction temperature (Tj) for given power maps for both the cases. Mesh sensitivity analysis is carried out with temp varies in the range of +/- 1 ° C; coarse meshing is used for the analysis. Parameters such as thick nesses of TIM1 and TIM 2, thermal conductivities of TIMs and convective transfer coefficient are calculated to satisfy the given package conditions. All the material properties are applied as per the material property data. Total power of 115 W is applied over a die as per the given power maps. A (h) of 1200 W/m2 °C is used on the top of package for the analysis. Once baseline cases for given non-uniform power maps are carried out, an optimization study is carried out to see the effect of non-uniform power on the maximum junction temperature. Percentage variation in the optimized temperature is plotted against baseline temperature. Design guideline will then be suggested for any number of power maps. Tool Ansys Workbench is used for the analysis and optimization study. Modeling Methodology Maximum junction temperature is simulated for the different power maps as mentioned above as baseline case. Initially optimization study is carried out for 4 x 4 and 6 x 6 power maps to define the number of functional blocks for any number of power maps [1]. For optimization study a functional blocks of 4, 6 and 12 different individual powers are used as a design variable for 6 x 6 power map. Blocks of 16 design variables are used for the case of 4 x 4 power map. Design explorer is used to analyze the optimization study. Functional block is a group of number of design variables (In this paper, different individual powers in a given power map). This analysis has no constraints placed on the redistribution of functional blocks. Figure 6 shows a solid model of divided die for four different cases. Figure 7 and 8 gives the different cases considered for optimization for two different power maps. A functional block of 4, 6 and 12 design variables can be seen on a 6 x 6 power map and 16-design variable in case of 4 x 4 power map as a test cases for optimization study. This study is then extended for all other power maps to get an optimized junction temperature. The best possible Tj max reduction could thus be found. In reality (and at a later date) constraints must be placed regarding the maximum separation of any 2 (or more) functional blocks to satisfy electrical timing and compute performance requirements. Ansys Design Xplorer is a powerful tool for designing and understanding the analysis response of parts and assemblies. Design Xplorer is based on Design of Experiment (DOE) and various optimization methods, and uses parameters as its basic language. These parameters can come from Simulation, Design Modeler, and various supported CAD systems. DOE is a technique used to determine the location of sampling points. There are several versions of design of experiment available in engineering literature. These techniques all have one common characteristic: they try to locate the sampling points such that the space of random input parameters is explored in the most efficient way, or obtain the required information with a minimum of sampling points. Sample points in efficient locations will not only reduce the required number of sampling points, but also increase the accuracy of the response surface that is derived from the results of the sampling points. Design Xplorer uses a central composite design, which combines one center point, points along the axis of the input parameters, and the points determined by a fractional factorial design. [9,10] Design parameters such as input, derived and response parameters are defined to start the optimization. Different powers are the input parameters and maximum junction temperature is the response parameter. Using the DOE method the number of design points is directly related to the number of selected input Parameters. No of design variables are usability variables, which depend on number of input parameters. Automatic design points are created using central composite design theory. Once it runs for the entire design points goal driven optimization is carried out to extract the desired results. In this case goal is to have summation of all the individual powers in an assigned functional block should be same with keeping the individual power distinct to lower down maximum junction temperature. Numbers of design variables are restricted to 18, which allow performing two different types of study on 6 x6 and 4 x 4 power maps. A combination study is carried out for the earlier one while first hand study is carried out for the later one. Once this study is carried out a graph of percentage variation change in optimized temperature is plotted against baseline case for different power maps. From this, guidelines are set for distribution of power, which will help to get comparable values of optimized temperature for a realistic power map i.e. 30 x 30. Following is a study shown for two typical cases. Case I: 6 x 6 Power map. As shown in the power map, functional blocks of 4, 6 and 12 are created to study its effect on the overall junction temperature. A combination of theses 3 methods will then be used to optimize the maximum junction temperature. These different cases are chosen randomly to account for variations of individual powers. Once data for individual cases of different functional blocks is extracted, a combination for best cases is selected to come up with optimized power map for 6 x 6. Case II: 4 x 4 power map for this power map, all the 16 different individual powers are grouped in a single functional block to optimize the design. This attempt will come up with design in a single attempt. Results and discussions Table 2 gives the various values of maximum junction temperature (baseline and optimized) with a percentage variation for all different power maps. Figure 9 and 11 shows the temperature distribution for original power map and optimized one for 6 x 6 case. Figure 10 and 12 shows the graph of power distribution after optimization study for 6 x 6 case as a test case. Original power map clearly shows the hot spots in the center with non-uniform temperature all over the area of the die. With optimized case, temperature is distributed more evenly over the area of the die. Figure 13 shows temperature distribution for optimized one for different cases such as 5,8,10 and 15. It can be seen that temperature distribution shows huge temperature drop within the chip after optimization. Figure 14 shows effect on maximum junction temperature for base and optimized cases for different power maps. Base line (original) temperature goes on increasing as the power map matrix number increases. This is possible due to the required uniform distribution of temperature for the higher power map matrices. Figure 15 shows effect on percentage variation change in optimized temperature on optimized temperature compared to baseline case. With the optimized temperature, range of 5 % to 13 % drop in temperature is achieved compare to original temperature for different cases of power maps. As the number of design variables increases, a significant drop in temperature can be possible for higher functional blocks. Increase in the percentage variation change in optimized temperature for ascending power maps is a key example of this fact. Interchanging locations of highest power with lowest power significantly lowers the maximum junction temperature. Low powers are distributed over periphery as compared to high powers. Groups of high powers, which are located near the center, are more responsible for optimization within the die. Functional blocks of wide range of powers are more effective as compared to blocks of same range. As power map matrix increases control over optimization enhances because of different levels of individual powers within that power map. High powers are distributed to various locations to form group of wide range of high and low powers. These design guidelines will be helpful to get the optimized junction temperature for a realistic power map case of 30 x 30 with 900 different functional blocks. Summary and Conclusion Thermal based optimization of functional block distributions in a non-uniform powered die is carried out using Ansys Workbench. In this study, in order to model the non-uniform power dissipation on the silicon chip, the chip surface area is divided into a various cases such as 3 x 3, 4x 4, 5 x 5, 8 x 8, 10 x 10, 12 x 12 and 15 x 15 of power matrix with a matrix space representing a distinct functional block with a constant heat flux. Finally, using a FEM code, an optimization of the positioning of the functional blocks relative to each other was carried out in order to minimize the junction temperature Tj. With these many power maps trend for the data is evaluated which helps to draw some design guideline for a typical die configuration i.e. 30 x 30. With the optimized temperature, range of 5 % to 13 % drop in optimized temperature is achieved compare to original temperature for different cases of power maps. As the number of design variables increases, a significant drop in temperature can be possible for higher functional blocks. Increase in the percentage variation change in optimized temperature for ascending power maps is a key example of this fact. Interchanging locations of highest power with lowest power significantly lowers the maximum junction temperature. Low powers are distributed over periphery as compared to high powers. Groups of high powers, which are located near the center, are more responsible for optimization within the die. Functional blocks of wide range of powers are more effective as compared to blocks of same range. As power map matrix increases control over optimization enhances because of different levels of individual powers within that power map. This analysis has no constraints placed on the redistribution of functional blocks. The best possible Tj max reduction could thus be found. In reality (and at a later date) constraints must be placed regarding the maximum separation of any 2 (or more) functional blocks to satisfy electrical timing and compute performance requirements. With following these design guidelines and key points further optimization study can be very effective for a realistic power map case of 30 x 30 with 900 different functional blocks. References 1. Abhijit Kaisare, Dereje Agonafer, A. Haji-shiekh, Greg Chrysler and Ravi Mahajan, “Thermal based optimization of functional block distributions in a non-uniformly powered die,” published in InterPACK conference, 2005. 2. Teck Joo Goh, A.N. Amir, Chia-Pin Chiu and J. Torresola, "Novel thermal validation metrology based on non-uniform power distribution for Pentium(R) III XeonTM cartridge processor design with integrated level two cache,"51st Electronic Components and Technology Conference, 2001, pp. 1181-1186. 3. Teck Joo Goh, "Thermal methodology for evaluating the performance of microelectronic devices with non-uniform power dissipation," 4th Electronics Packaging Technology Conference, 2002. pp. 312-317. 4. V. Gektin, Ron Zhang, M. Vogel, Guoping Xu and M. Lee, "Substantiation of numerical analysis methodology for CPU package with non-uniform heat dissipation and heat sink with simplified fin modeling," Thermal and Thermomechanical Phenomena in Electronic Systems, 2004, pp. 537-542 Vol.1 5. K.K. Sikka, "An analytical temperature prediction method for a chip power map," Semiconductor Thermal Measurement and Management Symposium, 2005, pp. 161-166 6. M.S. June and K.K. Sikka, "Using cap-integral standoffs to reduce chip hot-spot temperatures in electronic packages," Thermal and Thermomechanical Phenomena in Electronic Systems, 2002, pp. 173-178. 7. Zhiping Yu, D. Yergeau, R.W. Dutton, S. Nakagawa and J. Deeney, "Fast placement-dependent full chip thermal simulation," VLSI Technology, Systems, and Applications, 2001, pp. 249-252. 8. Ravi Mahajan, Raj Nair, V. Wakharkar, “ Emerging Directions for packaging technologies,” Intel Technology Journal, Q2, 2002 9. [S.G. Jagarkal, M.M. Hossain, D. Agonafer, M. Lulu and S. Reh, "Design optimization and reliability of PWB level electronic package," Thermal and Thermomechanical Phenomena in Electronic Systems, 2004, pp. 368-376 Vol.2. 10. Ansys Workbench (9.0) reference manual
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